1. Field of the Invention
The present invention relates in general to the field of electronic and logical circuits, particularly application-specific integrated circuits (ASICs) and, more particularly, to a method for temporally limiting and separating access instances between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip and an associated circuit arrangement, where the circuit arrangement has at least one master unit, at least one subordinate slave unit and a network-on-a-chip bus system (NoC) for a connection between the master and the slave unit, and where the access instances between the at least one master unit and the at least one slave unit are carried out on communication paths provided by bus interfaces of the network-on-a-chip bus system.
2. Description of the Related Art
Nowadays electronic circuits that are realized as “integrated circuits” are an important basis for all kinds of electronics. Typically, such electronic circuits or systems comprise electronic components or electronic circuits or integrated circuits (ICs) connected by wires to one another and accommodated on a single substrate (e.g., a semiconductor substrate). Such integrated circuits often consist of a large number of components or circuit groups of different types and connecting conductor tracks on or in a single-crystal substrate. By means of this integration, therefore, a wide range of functionalities and uses can be made available in a small space. In this way, it becomes possible to realize a plurality of uses (e.g., in mobile devices, SIM cards, RFIDs, or mobile telephones) in a simple and economical manner. Integrated circuits that have been created for special uses are also known as application-specific integrated circuits or ASICs.
As a result of continuing miniaturization of devices and an increasing level of integration, whole systems, such as with processors, controllers, memory components (e.g., ROMs, or RAMs) power management and other components, are accommodated on a “chip”. Such systems are known as one-chip systems or as systems-on-a-chip or systems-on-chip. Systems-on-a-chip are used, in particular, where small dimensions are required with a relatively high power and a wide variety of uses. In a system-on-a-chip, typically, a large part of the functions of the system is integrated on a chip, i.e., on a semiconductor substrate. Nowadays, designs of such systems-on-a-chip are often based on already existing and/or bought components, “IP core units” or “IP blocks”, such as processors, controller units, or peripheral blocks which, for example, are acquired as finished units or via design license for use in a system-on-a-chip. Units for the system-on-a-chip that are lacking can then be developed, for example, for the finished ASIC.
For the organization of the different units and for distribution of access instances, or tasks, between the units of the system-on-a-chip, the “master-slave concept” is frequently used. Herein, the respective tasks are distributed between higher-order units (the “master units”) and lower-order units (the “slave units”) and access to common resources (e.g., memory units) or use of a bus system is regulated. Preferably, the master-slave concept comes into use when a control and/or task distribution is taken over by at least one unit, e.g., a processor, or controller, as the master unit for at least one other component (e.g., special processors, or peripheral units) or access instances to at least one other unit (e.g., memory unit, or bus system) is regulated.
The units of the system-on-a-chip (e.g., the master and slave units) are internally connected via a bus system, where particularly in complex systems-on-a-chip, hierarchical or at least segmented bus systems are used. A bus system of this type can comprise, for example, a fast bus system, a slower peripheral bus and a register or control bus. The “network-on-a-chip bus system”, or NoC, herein represents a starting point for a design of flexible and efficient connections for the access instances between the IP blocks or master and slave units (e.g., processor, controller units, or peripheral blocks) of a system-on-a-chip. In a network-on-a-chip bus system, the information or access instances are not exchanged between the individual units of the system-on-a-chip via an internal bus, but via a layered bus architecture that is conceived as a network with distributor sites. Access by one unit to another unit of the system-on-a-chip on a path from a source unit to a target unit can be connected as a point-to-point connection or a multipath connection via a plurality of links as, for example, during “routing” in a packet-switched network. By means of the network-on-a-chip bus system, bus participants with master or slave functionality, i.e., bus agents of master units and/or slave units are connected via corresponding bus interfaces or “ports”, particularly initiator ports and target ports. These ports correspond to access addresses and, thus, a communication path from a source address to a target address via the network-on-a-chip bus system can be specified therewith and can thus be used for the routing.
Frequently, high security requirements are placed on systems-on-a-chip. It is therefore necessary to control access instances between the master and slave units via the network-on-a-chip bus system or, if relevant, spatially and temporally to limit and separate them, for example, in accordance with security concepts known from aviation and space technology, in order, for example, to be able to implement applications with different security relevance or security-relevant and non-security-relevant applications on one hardware platform or on a system-on-a-chip. Spatial limiting and separating of access instances via the network-on-a-chip bus system (this means, for example, that for the security-relevant applications (spatially) other address regions or bus interfaces are used than for non-security relevant applications) can be realized, for example, with the support of a “memory protection unit” (MPU) for commercially obtainable network-on-a-chip bus systems that do not usually have such security possibilities. A memory protection unit (MPU) is integrated for access control, e.g., in CPU units for a commercially available system-on-a-chip. Aside from other tasks, for example, memory protection tasks are regulated by the MPU and thus access to individual memory regions or, for example, bus interfaces or ports of the network-on-a-chip bus system can be controlled or blocked for particular units or access types (e.g., write access). However, via an MPU, for example, no temporal limiting, control and/or separating of access instances is permissible with commercially available network-on-a-chip bus systems.
Temporal separating of access instances to individual bus interfaces or address regions of the network-on-a-chip bus system have conventionally only been realized, for example, in application-specific proprietary solutions as, for example, in a “time-triggered network-on-a-chip” that has been developed in the context of the ACROSS research project and which is described, for example, in the publication by Martin Schoeberl, “A Time-Triggered Network-on-Chip”, Institute of Computer Engineering, Vienna University of Technology, Austria, 2007. This publication describes a time-triggered network-on-a-chip for an on-chip real time system, where a temporally predictable on-chip and off-chip communication is made available by the network-on-a-chip. The “time-triggered architecture” from the domain of real time systems is used on a chip-internal communication or the network-on-a-chip bus system. However, the network-on-a-chip bus system is designed and developed herein specifically for the requirements of the real time system or for the specific system-on-a-chip. However, this has the disadvantage of relatively long development times, greater effort and expense because no network-on-a-chip bus systems available on the market can be used. This also means that for systems-on-a-chip in which, for security and/or technical reasons, a temporal limiting and separating of access instances via the network-on-a-chip bus system is required, this must be specially developed.